[Tccc] CFP: 5th IEEE M2A2 held with 11th IEEE ISPA, Melbourne, Australia, 16-18 July, 2013
Houcine Hassan
huseinatdisca.upv.es
Wed Apr 24 07:13:09 EDT 2013
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Call for Papers
The 5th IEEE International Workshop on Multicore and Multithreaded
Architectures and Algorithms (M2A2 2013)
In conjunction with
The 11th IEEE International Symposium on Parallel and Distributed Processing
with Applications
http://anss.org.au/ispa2013/
Melbourne, Australia, 16-18 July, 2013
======================================================================================================
Scope:
Multicore systems are dominating the processor market ranging from embedded to
high-performance systems. Currently some processors integrate more than ten
cores and, as the node shrinks in future technology generations, it is expected
that the number of cores will continue increasing in future manufactured
systems.
To take advantage of the high number of cores efficient load balancing and
scheduling policies or strategies are required. In addition, it remains a
challenge to identify and productively program applications for these systems
with a resulting substantial performance improvement.
On the other hand, the system designer must trade off performance versus power
consumption, which is a major concern in current microprocessors. Therefore,
current design must focus on new architectures or architectural mechanisms
addressing this tradeoff.
Finally, most real-time embedded applications are requiring high-performance
computing and multicore and multithreaded processors are becoming the typical
design choice.
The aim of this workshop is to provide a forum for engineers and scientists to
address the resulting challenge and to present new ideas, applications, and
experience on all aspects of multicore and multithreaded systems.
Authors are invited to submit high quality papers representing their original
work in (but not limited to) the following topics targeting multicore
multithreaded processors:
* Multicore and multithreaded architectures
* Power-aware multicore architectures and computing
* Embedded multicore real-time systems
* Scheduling and load balancing
* Multicore programming
* Parallel and distributed algorithms
Paper Submission and Publication:
Submit original unpublished papers in PDF formats at the submission system:
https://www.easychair.org/conferences/?conf=m2a22013. All submitted manuscripts
will be reviewed at least by three expert reviewers. Submissions will be judged
on originality, technical strength, quality of presentation, and relevance to
the workshop scope.
All accepted papers will be included in the ISPA-2013 workshop proceeding
published by IEEE Computer Society (indexed by EI). The length of the
camera-ready manuscripts will be limited to 8 pages in IEEE CS proceedings
paper format. Authors of accepted papers, or at least one of them, are
requested to register and present their work at the conference, otherwise their
papers will not be published.
Distinguished papers accepted and presented in M2A2 2013, after further
revisions, could be considered for publication in special issues of SCI indexed
international journals.
Important Dates:
May 7, 2013: Paper Submission Due
May 16, 2013: Notification of Acceptance/Rejection
May 18, 2013: Camera-Ready Due
July 16-18, 2013: Workshop Takes Place
General Co-Chairs:
Houcine Hassan, Spain
Julio Sahuquillo, Spain
Steering Committee:
Laurence T. Yang, Canada
Jong Hyuk Park, Korea
Program Committee:
Hideharu Amano, Japan
Hamid R. Arabnia, USA
Saddek Bensalem, France
Rabie Ben-Atitallah, France
Luis Gomes, Portugal
Antonio Gentile, Italy
Roberto Giorgi, Italy
Zonghua Gu, Hong Kong
Rajiv Gupta, USA
Shih-Hao Hung, Taiwan
Eugene John, USA
Sebastian Lopez, Spain
Smail Niar, France
Yoshimasa Nakamura, Japan
Sabri Pllana, Austria
Sander Stuijk, Netherlands
Zili Shao, Hong Kong
Kostas Siozios, Grece
Kenjiro Taura, Japan
Sami Yehia, France
Zhu Yongxin, China
Yang Xiang, Australia
Contact information:
Houcine Hassan (hus... at disca.upv.es)
Julio Sahuquillo (jsahu... at disca.upv.es)
Department of Computer Engineering.
Universitat Politecnica de Valencia.
Camino de Vera, 14
46022 Valencia, Spain
_______________________________________________
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